RTL Design Engineer
A broad career platform- Cross regional and multi business development opportunities, equal achievement for everyone.
A free working atmosphere- Flexible working hours and equal communication mechanism.
Superior work benefits- Rich rewards and competitive remuneration
ThunderSoft is a provider of operating system technologies, superior products and solutions, experts in mobile, IoT, automotive, and enterprise. Founded in 2008, through ThunderSoft’s expertise in edge intelligence and operating systems including Android, Linux, Windows and others, a profound middleware, application, and algorithm technology portfolio, strategic partnerships with key semiconductors, components, terminals, software and Internet vendors, and mobile carriers, give us a unique vertical integration advantage across industries.
ThunderSoft is a value-added scaling partner, bringing our customers with innovative, reliable, and commercial-ready products and solutions for the fields of IoT and Intelligent connected vehicle. ThunderSoft has established joint ventures individually with Qualcomm, Arm and Intel. Meanwhile, the company operates joint laboratories with Qualcomm, Intel, Microsoft, Arm, Samsung, and Sony, among many others.
Headquartered in Beijing, Thundersoft operates 25 R&D centers and offices globally in Beijing, Nanjing, Chengdu, Chongqing, Wuhan, Xian, Shenyang and Dalian, Tokyo, Seoul, Shanghai, Shenzhen, Hong Kong, Taipei, Silicon Valley, and Helsinki. We can provide global customers with convenient and efficient technical services and local support.
If this is a journey you’d like to embark on, keep reading!
In this position you will:
Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs.
Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers.
Providing high-quality RTL description, including assertions, for the design.
Formal tools and static checkers will be used to guarantee RTL quality.
Supporting design verification to insure bug-free first silicon.
Driving functional and code coverage as well as timing closure for your designs.
Supporting silicon bring-up, performance and power characterization
RTL design using Verilog or System Verilog, assertion writing
Design of state machines, data paths, arbitration and clock domain crossing logic
Logic synthesis, timing constraints
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
Prior experience in DDR PHY design and mixed-signal environment is a plus
Open for fresh graduate